A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs.