A set of tools is provided herein that produces useful, proven, and
correct integrated semiconductor chips. Having as input either a
customer's requirements for a chip, or a design specification for a
partially manufactured semiconductor chip, the tools generate the RTL for
control plane interconnect; memory composition, test, and manufacture;
embedded logic analysis, trace interconnection, and utilization of spare
resources on the chip; I/O qualification, JTAG, boundary scan, and SSO
analysis; testable clock generation, control, and distribution;
interconnection of all of the shared logic in a testable manner from a
transistor fabric and/or configurable blocks in the slice. The input
customer requirements are first conditioned by RTL analysis tools to
quickly implement its logic. The slice definition and the RTL shell
provides the correct logic for a set of logic interfaces for the design
specification to connect. The tools share a common database so that
logical interactions do not require multiple entries. The designs are
qualified, tested, and verified by other tools. The tools further
optimize the placement and timing of the blocks on the chip with respect
to each other and with respect to placement on a board. The suite may be
run as batch processes or can be driven interactively through a common
graphical user interface. The tools also have an iterative mode and a
global mode. In the iterative mode, one or more of the selected tools can
generate the blocks or modify a design incrementally and then look at the
consequences of the addition, or change. In the global mode, the
semiconductor product is designed all at once in a batch process as above
and then optimized altogether. This suite of generation tools generates
design views including a qualified netlist for a foundry to manufacture.