An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.