Mode register setting methods and apparatuses for semiconductor devices
are provided in order to suppress a limit in the frequency at which a
mode register of a semiconductor device operates from occurring before
the semiconductor device carries out a typical write or read operation,
as the frequency at which the semiconductor device operates increases.
The mode register setting methods and apparatuses may be applied, for
example, to DDR-type semiconductor devices. If a chip selection signal
/CS maintains a logic low level for at least a first amount of time, a
semiconductor device may initiate a clock-independent mode register
setting operation. In the clock-independent mode register setting
operation, a mode register set (MRS) command and an MRS code bit may be
sampled when the logic level of a data strobe signal applied to the
semiconductor device transitions from a logic low level to a logic high
level. Therefore, it is possible to solve the problem of restrictions
regarding the operating frequency of the mode register of the
semiconductor device by performing a test mode register setting operation
independent of a clock signal applied to the semiconductor device.