A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile semiconductor memory cells arranged therein, the first and second cell arrays being disposed in the direction of each bit line for transferring cell data and physically independent of each other; a sense amplifier disposed between the first and second cell arrays to be common to them; and a decode circuit configured to select a memory cell in the first and second cell arrays in accordance with address assigned to the first and second cell arrays in such a way that the first and second cell arrays serve as one memory plane in logic.