A PMOS non-volatile memory array using SONOS transistors having program
and erase threshold voltages for representing digital logic states of
zero and one and selected to optimize read disturb characteristics. The
threshold voltages are linearly convergent and separated by at least 0.5
volts for a charge retention time of at least 10 years, with the
threshold voltages defining a window wherein a read voltage for selected
memory transistors can be held flat and not intersect the threshold
voltages. The lower threshold is selected to be at a zero charge state
for one of the two logic levels of the memory.