Embodiments of the present invention provide a design for handling
register overflow in a CPU having parallel registers. In an embodiment,
spill code generated by a registers allocator may be analyzed to identify
register spill instructions that can be associated. Register spill
instructions that can be associated may be rewritten as parallel spill
instructions, and the corresponding register spills may be configured for
storage into memory in a manner permitting them to be loaded back to the
registers in parallel.