Providing a signal processing method for image synthesis with reduced computation load, a signal processor circuit for image synthesis with reduced computation load which allows manufacturing at a low production cost, and imaging apparatus which uses the signal processing method and the signal processor circuit. The signal processor circuit includes: a table storage area for storing an LUT; a table overwriting section for overwriting an LUT written into the table storage area with another LUT; and an arithmetic operation section for performing arithmetic operation on a first digital signal or a second digital signal based on the LUT written into the table storage area each time an LUT is written into the table storage area and synthesizing the first digital signal and the second digital signal.