Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal. An output of the first three-input OR gate is connected to an input of the first NAND gate. The second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal. An output of the second three-input OR gate is connected to an input of the second NAND gate. A first output signal of the first NAND gate is connected to another input of the second NAND gate and a second output signal of the second NAND gate is connected to another input of the first NAND gate.