A method of placing and routing an integrated circuit design includes
generating an initial placement and routing for at least a portion of an
integrated circuit design. The initial placement and routing of the
integrated circuit design is analyzed to find a critical location and is
partitioned into a series of nested shells. Each shell surrounds the
critical location and each preceding shell. An ordering of the shells and
at least one of a timing constraint and an area constraint are selected
for each shell. Each shell is placed and routed in the order selected
according to the timing constraint and area constraint.