The invention relates to a semi-conductor component test procedure, as
well as to a semi-conductor component test device with a shift register,
which comprises several memory devices from which pseudo-random values
(BLA, COL, ROW) to be used for testing a semi-conductor component are
able to be tapped and emitted at corresponding outputs of the
semi-conductor component test device, whereby the shift register
comprises at least one further memory device, from which a further
pseudo-random value (VAR) is able to be tapped and whereby a device is
provided, with which the further pseudo-random value (VAR) can
selectively, if needed, be emitted at at least one corresponding further
output of the semi-conductor component test device.