A semiconductor memory device includes a page buffer circuit and an
arrangement of memory elements each including: a gate electrode provided
on a semiconductor layer with an intervening gate insulating film; a
channel region provided beneath the gate electrode; a diffusion area
provided on both sides of the channel region, having an opposite polarity
to the channel region; and a memory functioning member provided on both
sides of the gate electrodes, having a function of storing electric
charge. The page buffer circuit provides a common resource shared between
a memory array controller and a user. The page buffer circuit has two
planes containing random access memory arrays. The page buffer circuit
also includes a mode control section to facilitate access to the planes
over a main bus in user mode and access to the planes by the memory array
controller in memory control mode.