Disclosed is a key generator, which assures the security of a key by preventing a circuit designer and other persons from readily knowing the value of the key. Random number generator circuits (51, 52, 53 and so on) generate random numbers respectively in accordance with different clocks (CLK1, CLK2, CLK3, and so on). An arithmetic circuit (59) operates on the random numbers generated from the random number generator circuits (51, 52, 53 and so on) to generate an N-bit random number RA as the output from a random number generator (50). This N-bit random number is RA acquired via a key selector (43), and latched into a key register (45) in accordance with an acquisition enable signal EN from a timing monitoring counter (47), which is driven by a clock CLKA other than clocks CLK1, CLK2, CLK3, and so on, to obtain a hardware key, which is a unique secret key.