A hierarchical representation encapsulates the detailed internal
composition of a sub-circuit using the notion of a cell definition (a
CellDef). The CellDef serves as a natural unit for operational reuse. If
the computation required for the analysis or manipulation (e.g. parasitic
extraction, RET, design rule confirmation (DRC), or OPC) based on a
CellDef or one cell instance can be applied, with no or minimal
additional effort, to all or a significant subset of other instances of
the cell, very substantial reduction in computational effort may be
realized. Furthermore, a hierarchical representation also allows for the
partitioning of the overall analysis/manipulation task into a collection
of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed
across a large number of computational nodes on a network for concurrent
execution. While this may not reduce the aggregate computational time, a
major reduction in the overall turnaround time (TAT) is in itself
extremely beneficial.