A unit and a method of programming mounted programmable memories by a programming boundary scan component/unit being directly coupled to the programmable memory and directly coupled to a boundary scan test system. Directly coupling the memory to the programming boundary scan component Thereby eliminates having to serially clock information to and from the programmable memory through a number of other boundary scan components/units. The drive routines for programming the programmable memory by means of a boundary scan test system only needs to be modified as to the length of the serial boundary scan cell chain.

 
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< System, method and storage medium for providing a high speed test interface to a memory subsystem

> Switch control apparatus, semiconductor device test apparatus and sequence pattern generating program

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