In a multiprocessor environment, by executing cache-inhibited reads or
writes to registers, a scan communication is used to rapidly access
registers inside and outside a chip originating the command. Cumbersome
locking of the memory location may be thus avoided. Setting of busy
latches at the outset virtually eliminates the chance of collisions, and
status bits are set to inform the requesting core processor that a
command is done and free of error, if that is the case.