A memory system incorporates shared redundant memories and has a shared
redundant memory architecture. The memory system includes a modified
memory to be used as a shared redundant memory between memory systems.
These memory systems may have several smaller memories forming a single
logical memory or various memories in close proximity on an integrated
circuit system. The shared redundancy is achieved by adding a comparator
to the redundant element for comparing between the faulty address and the
system address and performing a memory operation based on the comparator
output. As the redundant memory operations are performed in parallel to
the memory structures, setup and hold times are reduced. Shared
redundancy also results in reduced integrated circuit area.