A simplified architecture is disclosed for ADC conversion of received in-phase I and quadrature Q signals. Circuit area is substantially reduced by sharing a single ADC to convert both signals, switching the ADC input alternately between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of a single ADC. Aligning includes delaying one of the digital signals, and interpolating the other one of the digital signals in a low pass filter so as to compensate for the phase difference introduced by the sampling during the first and second time intervals. The first and second time intervals are equal to a predetermined ADC sample period corresponding to a sample clock cycle. Delaying the first digital signal includes a delay of 1/2 clock cycle.