In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which value is loaded in the associated latch. A controlling value set, indicating at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted, is also defined in one or more files. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.