A normal write data selection circuit operates in the normal operation
mode, and thus outputs data received through external data terminals to
any one of regular cell arrays selected according to an address. A test
write control circuit operates in the test mode, and thus writes test
data into a regular memory cell at a location corresponding to a location
of a parity memory cell into which test parity data are written in each
of regular cell arrays. Therefore, since a common test pattern can be
used to test both the regular memory cell and the parity memory cell,
test cost can be curtailed.