Bus transactions in a memory controller are scheduled by storing a set of
configuration parameters that define a bus scheduling policy, generating
values of a set of dynamic cost functions for each bus transaction,
ordering the bus transactions in accordance with the bus scheduling
policy to produce ordered bus transactions and generating a memory
transaction that is derived from the ordered bus transactions. The memory
controller includes one or more control registers for storing the set of
configuration parameters, a bus interface operable to capture bus
transactions from applications, a set of buffers operable to store the
bus transactions and the set of dynamic cost functions and one or more
registers operable to store the statistical data and a cost policy. The
memory controller selects the order of the bus transactions based on an
arbitration and selection policy and generates memory transactions to an
external memory.