A FIFO circuit includes a write counter circuit, a memory circuit, a read
counter circuit and a selector circuit. The write counter circuit counts
a write clock signal during a valid period of input data, and outputs a
write counter value. The memory circuit stores the input data in response
to the write counter value. The read counter circuit counts a read clock
signal when a decision is made that the memory circuit includes data that
has not yet been read out, and outputs a read counter value. The read
selector circuit reads data from the memory circuit in response to the
read counter value. A small scale FIFO circuit can be obtained.