A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.

 
Web www.patentalert.com

< Network controller and method to support format negotiation between interfaces of a network

> Processing of received data within a multiple processor device

~ 00420