The discrimination phase margin monitor circuit (10) of the present
invention comprises a first discrimination circuit (11 and 12)
discriminating an input data signal using a clock signal extracted from
the input data signal, a second discrimination circuit (13 and 14)
discriminating the input data signal using a clock signal with a
frequency different from that of the clock and an operation circuit (15
and 16) calculating the exclusive OR of the output signal of the first
discrimination circuit and that of the second discrimination circuit and
obtaining a phase margin monitor output signal by averaging the exclusive
ORs.