An A/D conversion array for an image sensor, in which the number of amplifiers and capacitors are decreased, compared with the conventional cyclic type, and a function to cancel the noise generated in the pixel section of the image sensor is provided, so that the area and power consumption are decreased. After input signal Vin is supplied to C1 and held, a reset level is applied to Vin, whereby the signal is amplified by the ratio of C1 and C2 (C1/C2). An output is held in C1, and the output is A/D-converted by a comparator so that a control signal is generated by the conversion output and a switch is turned ON. The digital signal is converted into an analog signal, and the analog signal is subtracted from the signal held in C1. This signal is amplified and is subjected to A/D conversion again, and the same operation is repeated.

 
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> System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC)

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