Techniques for performing static and dynamic race logic analysis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) design source files of an IC design are compiled into a common design database, including recording full timing information of the IC design. A static race logic analysis is performed on the common design database to reveal all possible race logic in the IC design. A dynamic race logic analysis could also be performed on the common design database to reveal times and circuit locations where the race logic would occur when a physical IC chip for the IC design is implemented. A race logic analysis report is generated for the static and/or dynamic race logic analysis, where the race logic analysis report is used to eliminate race logic errors in IC designs, so as to render highest quality IC products that will not exhibit intermittent random failures in field operations.