A cache system comprises i (e.g., 2) groups of m (e.g., 2) ways and n (e.g., 2) sets of cache arrays, a set address decoder, a comparator, a cache address and cache management information. The set address decoder selects all or one of the i groups of cache arrays based on the cache address and cache management information, and selects a j-th set in the selected cache memories according to the cache address. The comparator selects a way from the selected set based on the cache management information, compares the block address of a cache block in the selected way with a requested block address to decide whether there is a cache hit or a miss, and select a replacement block based on LRU information

 
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> System and method for power efficient memory caching

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