A method and system to automate scan synthesis at register-transfer level
(RTL). The method and system will produce scan HDL code modeled at RTL
for an integrated circuit modeled at RTL. The method and system comprise
computer-implemented steps of performing RTL testability analysis,
clock-domain minimization, scan selection, test point selection, scan
repair and test point insertion, scan replacement and scan stitching,
scan extraction, interactive scan debug, interactive scan repair, and
flush/random test bench generation. In addition, the present invention
further comprises a method and system for hierarchical scan synthesis by
performing scan synthesis module-by-module and then stitching these
scanned modules together at top-level. The present invention further
comprises integrating and verifying the scan HDL code with other
design-for-test (DFT) HDL code, including boundary-scan and logic BIST
(built-in self-test).