Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

 
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< Memory device and sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations

> Semiconductor memory

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