A method and apparatus for capturing and using design intent within an IC
fabrication process. The design intent information is produced along with
the design release by a design company. The design release and design
intent information are coupled to an IC manufacturing facility where the
design release is used for producing the layout of the integrated circuit
and the design intent information is coupled to the equipment, especially
the metrology equipment, within the IC manufacturing facility. As such,
the design intent information can be used to optimize processing during
IC fabrication to achieve optimization of the critical characteristics
intended by the designer.