An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.