A data serializer includes a data aligner, two N-bit shift registers, a
2-1 multiplexer, and a driver, wherein N is the number of parallel input
data bits. Data is received and aligned by the data aligner, which is
arranged to drive odd and even data lines to a respective one of the
N-bit shift registers. One N-bit shift register is arranged to operate
with a clock that is 180 degrees out of phase with respect to the other
N-bit shift register. The frequency of the clock for each N-bit shift
register is related to an input clock frequency by a factor of N/2. The
multiplexer is arranged to alternate the selection of the N-bit shift
registers to provide the output signal. The output of the multiplexer
corresponds to a high-speed serial data stream that can be provided to a
driver such as LVDS, DVI, PPDS or RSDS drivers.