Separate read and write ports in a memory system allow simultaneous access
to a memory cell array by read and write operations. A single cycle
operation of a central processing unit coupled to a memory array depends
on a memory access capability providing simultaneous reading and writing
to different locations. A pair of pull-down transistor stacks connected
to memory cell latch loops allows a single selected pull-down stack of
the pair to toggle a memory cell latch loop to a desired data content
without any requirement for a precharge scheme. A single pull-down stack
of transistors connected to a memory cell latch loop provides a read port
with low input loading. A sense amplifier provides a mid-supply-level
precharging capability provided by a feedback device within a front-end
inversion stage. When not in a feedback mode, the front-end inversion
stage cascaded with a second inversion stage provides a rapid read
response.