A laminated ceramic capacitor including a capacitor body where internal electrodes and a dielectric layer are alternately laminated, and external electrodes are provided on the end faces thereof. In this capacitor body, high resistance layers are provided between the internal electrodes and dielectric layer. These high resistance layers contain a ceramic material, an element including at least one selected from Mn, Cr, Co, Fe, Cu, Ni, Mo and V, and/or a rare earth element.

 
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> Method of controlling mode register set operation in memory device and circuit thereof

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