A latency control circuit for use in a semiconductor memory device includes a precharge unit for outputting a precharge reset signal based on a refresh signal and a normal active signal, wherein the precharge reset signal is used for extending a latency during a burst read period which includes a refresh cycle; a refresh cycle detector for detecting the refresh cycle in response to a latency setting signal and the precharge reset signal to thereby output a latency extension signal; a latency decoder for decoding an external address to thereby output a plurality of preliminary latency signals; and a latency controller for outputting a plurality of latency signals in response to the preliminary latency signal and the latency extension signal.