A system for obtaining translation information from a data processing system transparent to the operation of a processor core of the data processing system. In one embodiment, the processor includes a processor core and memory management circuitry. The memory management circuitry stores translation information. The data processing system includes debugging circuitry for obtaining translation information stored in the memory management circuitry and for providing that information externally.

 
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> Scaling address space utilization in a multi-threaded, multi-processor computer

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