A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.