A control terminal section CON and an address terminal section ADDR of a test apparatus are respectively connected to those of a flash memory. A first to an (n-1) -th input and output terminal of the test apparatus are connected to data terminals of the flash memory. Further, an n-th and an (n+1)-th input and output terminal of the test apparatus are connected to a multifunctional terminal of the flash memory. The (n+1)-th input and output terminal is established as a dedicated terminal to receive data supplied to the test apparatus. The first to the n-th input and output terminal of the test apparatus are used to output the writing data to the flash memory, while the (n+1)-th input and output terminal is used to detect the completion signal output from the flash memory.