A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory built in self test sequencer module and providing satellite engine module coupled to the memory built in self test sequencer module, to the plurality of embedded memories and applying read and write protocols to the plurality of embedded memories based upon the particular read and write protocols of each of the embedded memories. The satellite engine module includes an instruction buffer and a sequence generation engine.