An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

 
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> Resistive memory device with improved data retention

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