An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.

 
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> Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

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