A sampling system is disclosed which measures high speed data signals by performing sampling events at intervals determined by a programmable DDS output frequency and a programmable counter. The reference frequency of the DDS is that of a clock signal that is synchronous with the data signal to be measured. The present invention is able to arrange the sample points to form an eye diagram of the input signal. In addition, the present invention is capable of sampling synchronously with the data clock and controlling the phase of the synthesized signal such that the samples are localized around the rising and falling edges of the data waveform. The present invention is thereby able to determine the location of the edges of the data signal and analyze the deterministic jitter of the waveform.

 
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> Processor bus for performance monitoring with digests

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