With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction in a master thread being executed by a predetermined processor and when forkable, the slave thread is forked into other processor and when not forkable, the fork instruction is invalidated to execute an instruction subsequent to the fork instruction by the predetermined processor and then execute a group of instructions of the slave thread by the predetermined processor.

 
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> Method and apparatus for reducing power consumption in an integrated circuit chip

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