A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated circuit) are designed. In an embodiment, a designer specifies various checkpoints associated with each design stage, and the specific information to be made available to a top level performing the validation. When each checkpoint is reached for a design block, the specified information is made available to the top level and the validation of the integrated circuit is performed up to that checkpoint. As a result, design closure of the integrated circuit can be obtained quickly.