In a telecommunications system, an arithmetic logic unit (ALU) that receives an input signal. The input signal includes a digital signal representative of an analog signal. The ALU selectively performs compression and decompression on the digital signal. The ALU comprises the following elements. A standard ALU component performs standard ALU operations on the input signal. An encoding unit selectively performs compression on the digital signal. A decoding unit selectively performs decompression on the digital signal. An instruction decoder receives and decodes an ALU instruction. An output selector selects a result from one of the standard ALU component, the encoding unit, and the decoding unit in accordance with the decoded instruction and provides the result as an output.