An electrostatic discharge (ESD) protection circuit in a semiconductor
integrated circuit (IC) having protected circuitry. The ESD protection
circuit includes a silicon controlled rectifier (SCR) having at least one
first type high dopant region coupled to a first reference potential of
the protected circuitry, and at least one second type high dopant region
coupled to a second reference potential of the IC. The SCR is triggered
by an external on-chip trigger device, which is adapted for injecting a
trigger current into at least one gate of the SCR.