The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core cell nodes and the second metal layer comprises power/ground. The RAM is also fabricated with metal junction points on the first metal layer in at least a portion of the intersections. Thereafter, the RAM is reconfigured to a ROM by forming vias between the intersections of the first and second metal layers over the junction points to connect the first metal layer to the second metal layer.

 
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> Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit

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