A chip protection register lock circuit uses a plurality of lock bits in a
lock bit register. If the register contains N bits, N/2 bits of the
register are coupled to an erase circuit and the remaining N/2 bits are
coupled to a programming circuit. After the chip protection register is
programmed, the group of N/2 bits coupled to the erase circuit are erased
and the remaining N/2 bits are programmed such that an alternating
pattern of logical ones and zeros are in the lock bit register. A read
and compare circuit generates a lock indication if the alternating
pattern is present.