A processor including a register file and method for computing flush masks
in a multi-threaded processing system provides fast and
low-logic-overhead computation of a flush result in response to multiple
flush request sources. A flush mask register file is implemented by
multiple cells in an array where cells are absent from the diagonal where
the column index is equal to the row index. Each cell has a vertical
write enable and a horizontal write enable. When a row is written to
validate that row's tag value, the column having an index equal to the
row selector is automatically reset (excepting the absent cell mentioned
above) . On a read of a row, a wired-AND circuit provided at each column
provides a bit field corresponding to other rows that have been written
since a last reset of the row, which is a flush mask indicating newer
tags and the selected tag.