There is provided a storage apparatus, which can continue processes to a host without making it recognize any soft errors as failure even if the errors occur in its microprocessor. The storage apparatus comprises: a plurality of host interface control circuits controlling data transfer with a host; a disk interface control circuit controlling data transfer with a physical memory device; a cache memory board storing the data temporarily; and a switch board connecting the host interface control circuits, disk interface control circuit, and cache memory board, wherein each of the host interface control circuits has two or more CPUs and when a soft error occurs in the CPU, data transfer process with the host is inherited to the CPU in which no soft error occurs, so that a reset process to the CPU in which the soft error has occurred is carried out.